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  1. alarm

    0下载:
  2. The red arrow showed the output became 8 when the measured temperature changed to 11°C. As shown by black arrow, the maximum output was 28. The program was run according to the proposed method.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-05
    • 文件大小:99.43kb
    • 提供者:jayjay
  1. comp

    0下载:
  2. The red arrow showed the output became 8 when the measured temperature changed to 11°C. As shown by black arrow, the maximum output was 28. The program was run according to the proposed method.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-04
    • 文件大小:111.97kb
    • 提供者:jayjay
  1. 8.3-LCD

    0下载:
  2. FPGA驱动LCD显示中文字符程序及状态机的使用-FPGA to drive the LCD display Chinese characters procedures and the use of the state machine
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-02
    • 文件大小:4.8kb
    • 提供者:林高办
  1. curtain

    0下载:
  2. The red arrow showed the output became 8 when the measured temperature changed to 11°C. As shown by black arrow, the maximum output was 28. The program was run according to the proposed method.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-30
    • 文件大小:112.49kb
    • 提供者:jayjay
  1. lighting

    0下载:
  2. The red arrow showed the output became 8 when the measured temperature changed to 11°C. As shown by black arrow, the maximum output was 28. The program was run according to the proposed method.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-06
    • 文件大小:89.3kb
    • 提供者:jayjay
  1. modulated_gen

    0下载:
  2. The red arrow showed the output became 8 when the measured temperature changed to 11°C. As shown by black arrow, the maximum output was 28. The program was run according to the proposed method.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-17
    • 文件大小:182.62kb
    • 提供者:jayjay
  1. RD1055_rev01.3

    0下载:
  2. NAND Flash Controller Reference Design RD10- NAND Flash Controller Reference Design RD1055
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-08
    • 文件大小:583.51kb
    • 提供者:akjfklaskdfj
  1. sata_controller_core_latest.tar

    0下载:
  2. The SATA2 core implements the Command, Transport and Link Layers of the SATA2 protocol and provides a Physical Layer Wrapper for the transceivers.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-06
    • 文件大小:53.46kb
    • 提供者:akjfklaskdfj
  1. vhdl

    0下载:
  2. 此程序为VHDL的四位比较器,两位输入,三位输出-This procedure the VHDL four comparators, two input, three output
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-23
    • 文件大小:1.31kb
    • 提供者:马付涛
  1. RAOM

    0下载:
  2. 此包为两个程序,一个为八三编码器,一个为RAM存储器,程序完全能运行-This package of two programs, one for 83 encoder, a RAM memory, the program is fully capable of running
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-11
    • 文件大小:928byte
    • 提供者:马付涛
  1. jiep

    0下载:
  2. 两个程序,其一为节拍发生器,其二为同步计数器-Two programs, one to beat generator, and the second synchronous counter
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-30
    • 文件大小:894byte
    • 提供者:马付涛
  1. NAND_Flash_Interface_DF

    1下载:
  2. actel NAND Flash Interface Design Example
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-12
    • 文件大小:2.48mb
    • 提供者:akjfklaskdfj
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