资源列表
shiyan7_12
- 设计一个数字时钟，具有按秒走时功能，能够分别显示小时（2位24小时）、分种（2位）、秒（2位）的功能，以及整点报警功能-Design a digital clock with seconds to go by when the function that displays hours, respectively (two 24-hour), minutes (2), second (2) function, and the whole point of the alarm function
ctc83
- 在文本编辑器中使用VHDL语言设计一个8-3编码器-In a text editor designed using VHDL, a 8-3 encoder
shiyan6_1
- 用vhdl语言设计液晶显示14行汉字的程序-Language design using vhdl line 14 character LCD display program
banjiaqi_t15
- 这是个半加器,是基于VHDL语言上的操作来实现的!-this is a banjiaqi
NIOS_UART
- NIOS_LED现成fpgaNIOS系统源代码，运行环境quartus II -NIOS_LED ready fpgaNIOS system source code, operating environment quartus II
FPGAandCPLDentry-leveldetailedstudymaterials
- fpga和cpld入门级详细的学习资料，内容很详细很全面。非常实用。-entry-level fpga and cpld detailed study information, the content is more comprehensive. Very useful.
ThetrainingcourseofXilinxcompany
- xilinx公司2007年上海培训课程资料，主要是PPT。非常好的资料-xilinx Shanghai in 2007 training material, mainly PPT. Very good information
Xilinx6EDKtest
- xilinx公司的官方资料，关于EDK试验的。很好的东西。-the company of xilinx official information
MLP-network-prior-t-th-FPGA-implementation
- 前向MLP网络的FPGA实现MLP network prior to the FPGA implementation-MLP network prior to the FPGA implementation
eda
- 计数器 此程序完成从零开始到9的计数功能呢个 用VHDL语言编写-counter you kan use the program to count from 1 to 9 and the program is free
sign_by_unsign_multiplication
- sign by unsign and sign by sign multiplication in verilog
ISE_lab16
- 使用VHDL语言设计数字钟。 数字钟由晶振、分频器、计时器、译码器、显示器等组成-Digital clock design using the VHDL language. Digital clock from the crystal oscillator, frequency divider, timer, decoder, display and other components