资源列表
FPGA-study
- FPGA学习基础,有一些开发的技巧，适合入门-basic study of FPGA，some useful skills，prepared for beginners
VHDL
- VHDL系统设计实例源程序集 VHDL系统设计实例源程序集-VHDL Design Example Design Example VHDL source set source set
cod_lab6_all
- 单周期cpu的流水线设计 是一个完整的工程- Monocycle cpu assembly line design
ADC_pico
- lkJHAKJCNKA A.LKJDLAMNCXLn akwjdNM.JDA. kjawdln ñ iajdlkjad alkjdkajd adjlkajsdlkn lqkwhdjlkalkdn añ lkjdlkajdlaj ñ klawjdlalknd añ lkjdñ laksjdncañ ñ alkjdñ qjekdja. lksajdñ la-lkJHAKJCNKA A.LKJDLAMNCXLn akwj
Prueba2
- lksajhdcla kajsdkjna cwkjelas-laksnc akjshdkj lAKJSKJD LAkhsdkq LKJALKF lkjhaskfnca elsjaf añ ljfa alñ ksjflj. añ djlkajd adffsdg-lksajhdcla kajsdkjna cwkjelas-laksnc akjshdkj lAKJSKJD LAkhsdkq LKJALKF lkjhaskfnca elsjaf añ ljfa
ADCyDAC
- kajsfdlva s.lkjflkamslv awlejfsfdlfkmalca welirfjlskmadf-lkawe gJAWELKFL-SMGF KEQRHJALFJal_ekJF SDLKGJAELJFGLA GÑ LAJFLKAN SFLKÑ AJWEÑ LKJFALÑ KWN FAWÑ LKEJFÑ LAWJG. asDAKJHWLkajhslkf slñ afk
urat_1
- VHDL进行串口通信的一种实现方法，供参考-VHDL Implementation of Serial Communication
vhdL
- VHDL多路选择器 （使用case语句）-VHDL multiplexer (using case statement)
verilog
- 北大verilog课件，Peking University verilog Courseware-Peking University verilog Courseware
123
- 系统介绍了数字开发系统平台FPGA设计中的部分技巧 对于FPGA开发研究人员具有一定的指导和帮助意义-Systematic introduction of digital development platform FPGA design techniques for FPGA development of some of the researchers have some sense of guidance and help
clock1
- 本程序用VHDL编写数字钟，具有定点报时，手动调整时间等功能，能下载到板子上显示时间。-This program written by VHDL digital clock, with a fixed broadcast, manually adjust the time and other functions, can be downloaded to display the time on the board.
states
- 红绿交通灯工作过程仿真，FPGA平台实现 -Red and green traffic lights work process simulation, FPGA platform