资源列表
usual-problems-about-niosII
- niosII中常见英文问题汇总！！很有用哦-English summary of the common problems niosII! ! Oh, very useful
GPSA
- FPGA低成本GPS信号模拟器设计GPS signal simulator designed low-cost FPGA-GPS signal simulator designed low-cost FPGA
Example-4-1
- FPGA中存储器设计实例，包括设定与仿真，适合初学者使用-FPGA, memory design examples, including the setup and simulation, suitable for beginners
Example-4-17
- 学习异步复位、同步释放电路建模的方法。异步复位、同步释放的具体设计方法很多，关键是如何保证同步地释放复位信号。本例的设计方法是在复位信号释放时，用系统时钟采样，然后将复位信号送到寄存器的异步复位端。-Learning asynchronous reset, synchronous release of circuit modeling approach. Asynchronous reset, synchronous release of many of the specific design,
Example-6-1
- 1. Example-6-1\FSM\state1目录下为一段式FSM描述方法源码 2. Example-6-1\FSM\state2目录下为两段式FSM描述方法源码 3. Example-6-1\FSM\state3目录下为三段式FSM描述方法源码 4. Example-6-1\FSM\ state_default目录下为添加了default默认状态的源码 -1. Example-6-1 \ FSM \ state1 directory FSM descr iption met
CRC
- 一個CRC-12計算的串入式電路並下載至FPGA電路板-FPGA CRC-16
seg
- 这是用verilog 编写的静态数码管实验，初级，实用，挺好的例程-It is written in verilog static digital test, primary, practical, very good routine
Synthesizable-Verilog-syntax
- 可综合的Verilog语法（剑桥大学，影印）.-Synthesizable Verilog syntax (Cambridge, photocopying).
Xia-Yu-Wen
- Verilog数字系统设计教程（夏宇闻）-Verilog Digital System Design Tutorial (Xia Yu Wen)
Verilog
- 经典fpga的verilog初级教程，适合于入门给学者-The initial tutorial fpga verilog classic, suitable for entry to the scholars
test-org
- Flosting point adder verilog HDL
part1
- VHDL 3-digit counter on LCD display.