资源列表
Parity_Gen_Source
- The Included files are the executed Output files of Parity Generator Ciruit
SAYEH
- Verilog 数字系统设计---综合、测试平台与验证 .书中源程序-cpu in verilog descr iption. include C language source
GCD_Verilog
- 利用Verilog语言写的采用更相减运算的球两个数的最大公约数-Using Verilog language written using a subtraction ball number two of the greatest common divisor
1602screen
- 实现用FPGA驱动1602显示屏显示字符的程序-Implemented in FPGA-driven character display program 1602
VHDL
- VHDL的100个简单实例，可以参考一下-100 a simple VHDL example, you can refer to
add
- 加法计算器，在vhdl下变成完成，包括仿真等。可以完整在quartus，maxplus等下运行-adder vhdl
my_orrrr
- FPGA上的一个或门实例程序，通过测试，可以直接运行在fpga开发板上。-An instance or door on FPGA program, through the test, can be run directly on the FPGA development board.
speak3
- 在FPGA上实现简易电子琴功能，再加上了一个实时时钟功能，时钟很稳定，很精准。-The realization of simple electronic organ function in the FPGA, coupled with a real time clock, the clock is very stable, very accurate.
RFID_UART
- 实现了rfid与fpga串口的数据通讯，fpga自发送-Achieve rfid serial data communication with the fpga, fpga from sending
EP1C3_12_3_VGA
- vga彩条信号显示控制，能实现方格彩条，横竖彩条-vga color bar signal control, to achieve grid color, horizontal and vertical color bar
modelsim-6.0
- 硬件描述语言仿真工具modelsim 6.0的附图详细教程-the detail tutorial of modelsim 6.0 with pictures
lizi
- 用标准的verilog实现的vga256色，实验，可以在电脑上是实现，用的就是家用的电脑显示器，可以清楚看到256se-this is a standard verilog experence which can dest the vga 256 color