资源列表
pong
- Verilog code pong the game
D_chufa
- 在QuartusII软件环境下，编写的移位寄存器的实现，包含仿真波形；-Quartusii software in the circumstances of the shift register, containing simulation waveforms
measure
- 脉宽测量电路，低电平有效，测量的最大脉宽为256拍，若超出则报溢出-Pulse width measurement circuit, active low, the maximum pulse width measurement 256 film, if overflow beyond the reported
CPLD-FPGA
- CPLD FPGA嵌入式应用开发技术白金手册配套源码-CPLD FPGA embedded application development technology platinum manual matching the source code
21POINT.tar
- 21点游戏的FPGA实现，使用VHDL语言，已经测试成功。-21-point game of the FPGA implementation
Chip_hardware_description_language_related_program
- 硬件描述语言相关芯片程序源码Chip hardware descr iption language-related program source code-Chip hardware descr iption language-related program source Chip hardware descr iption language-related program source code
pingpang
- 本实验在实验室实现了对于简易的乒乓球游戏的模拟，以发光二极管的移动来模拟乒乓球的移动，转向表示击球，并实现积分。-In this study, achieved in the lab for a simple table tennis game simulation, in order to light-emitting diodes to simulate the movement of table tennis movement, turning that ball and achieve
decode3_8
- 用verilog编写的三八译码器的演示程序，编程环境是xinlinx ise10.1-March Eighth prepared with verilog decoder demo, programming environment is xinlinx ise10.1
multi
- 基于Verilog HDL 的乘法器，可以实现一些功能的计算(Multiplier based on Verilog HDL)
fenpin
- verilog语言编写的分频程序，可以通过defpram实现任意整数任意占空比分频，有详细注释-divider verilog language program can be achieved through defpram arbitrary integer divide any duty, detailed notes
Cordic
- block-matching 3D filtering (BM3D) [2], and low-rank regularization [3], single-image based denoising performance has greatly improved, with image details well recovered when the image is slightly noisy. However, with the increase of noise le
2
- Computer hardware curriculum design, use QUARTUS II completed the experiment.