资源列表
chirp
- VHDL CODE Of chirp counter
rate
- 一个通过降低精度提高运算速度的8bit加法器设计，仅供参考-A improve processing speed by reducing the accuracy 8bit adder design, for reference only
ampliFM100W
- 100w Amplifier very powerful
websvn-filedetails
- SPI interface descr iption. REalise spi interface for VHDL code.
Micro8a-14oct02
- Micro8a - 一个简单的 8 位 VHDL CPU 核源代码-Micro8a- A Simple 8 bit VHDL CPU source code
FPGA
- vga的图像动态显示，用verilog编写，运行成功。对初学者很有帮助。-vga image dynamic, with verilog to write and run successfully. Useful for beginners.
yejingxianshi
- 基于FPGA的1602液晶显示器的Verilog源程序代码-FPGA Verilog source code based on the liquid crystal display 1602
shenyan
- 一个七段译码，一个异步复位计数器，一个melly机，我自己写的实验报告-a vhdl report,by a uestc student,
DDS_sin_of_square
- 双路DDS的设计与实现，幅值和频率可调，相对误差在 0.01之内-Design and implementation of dual DDS, adjustable amplitude and frequency, the relative error within 0.01
1024FFT(VHDL)
- 用VHDL实现1024的FFT，包含源文件和综合文件-Using VHDL 1024 FFT contains the source files and documents
POS_PHY_RTL
- VERILOG五POSPHY LEVEL3电路描述，可综合,已经过检验.
FIFO
- FIFO is accomplished with the code which is written using the language of verilog.FIFO is the means of first output while first input