资源列表
async_fifo
- verilog HDL写的异步fifo代码及测试平台，直接可用，可生成RTL代码-asynchronous fifo write verilog HDL code and test platform, directly available, can generate RTL code for
dds
- 基于fpga的函数发生器设计通过fpga实现正弦波输出-基于fpga的函数发生器
ddfs
- 使用单片机控制FPGA完成直接数字频率合成(DDFS),采用Keil C51-Complete single-chip FPGA to control the use of direct digital frequency synthesizer (DDFS), using Keil C51
EP1C3
- schematic altera EP1C12
BCD_COUNTER
- Binary Counting A binary counter can be constructed from J-K flip-flops by taking the output of one cell to the clock input of the next. The J and K inputs of each flip-flop are set to 1 to produce a toggle at each cycle of the clock input. For eac
synchronism_design
- fpga中往往会遇到跨时钟，或者异步时钟，这就需要涉及到时钟的同步问题。-often will be in the fpga experience across clock or asynchronous clock, which relates to clock synchronization issues
crc
- CRC校验原理，详细讲述CRC的数学模型和计算机实现-The CRC principles, a detailed account of the CRC mathematical models and computer implementation
das3580sch
- das3580开发板原理图，■ Altera CycloneII EP2C8Q208C8N 的FPGA器件； ■ EPCS4 – 4Mbit 串行配置器件； ■ JTAG和AS双模式下载口； ■ 512Kbyte 10ns级SRAM器件构成双数据通道； ■ Cy7c68013a_128axc高性能USB2.0控制芯片；-das3580 development board schematics, ■ Altera CycloneII EP2C8Q208C8N the FPG
7vhdl
- 16 进制段位数码译码扫描显示，用VHDL编写计数器并完成计数显示
counter_up_down
- VHDL语言写的可逆计数器，两路输入，可加可减-VHDL language of the reversible counter
4_Gesture_Sensor_Lab
- altera max10 手势传感器demo，2个传感器，nios2 实现-altera max10 Lab4 Gesture Sensor Lab，carry out with nios2
ARM7
- 用verilog编写的ARM7内核代码，通过modelsim仿真-With verilog code written in ARM7 core, through the modelsim simulation