资源列表
shiyan8
- 本设计利用可编程逻辑器件配以一个小扬声器设计了一个音乐发生器。-This design uses programmable logic device accompanied by a small speaker designed a music generator.
f_adder_4bit
- 四位二进制全加器，用原理图输入的形式实现，在Quartus II 5.1下编译通过。-4 binary full adder, with schematic input in the form of implementation, compiled in the Quartus II 5.1 adoption.
dianji
- 用verilog写的FPGA电机驱动程序，有需要的同学可以看看！-Written with verilog FPGA motor drivers, students need to take a look at!
forth1
- 计算机设计与实践实验，实现四位并行加法器，-Design and practice of computer experiments, to achieve four parallel adder,
61EDA_D807
- VHDL数频分频器设计 整数，奇数，偶数，半数等的分频 -VHDL design of an integer number of frequency divider, odd, even, half of the frequency, etc.
DDFS
- 本文档主要介绍了基于DE2和FPGA的DDFS设计，用的是altera的cyclone系列FPGA-This document describes the FPGA-based DDFS DE2 and design of the cyclone using a series of altera FPGA
SDRAM_CTR
- vhdl语言编写的fpga控制sdram的程序，包括仿真结果.-program of vhdl to control sdram in which includes the simulating results
shiyan_2_1
- 这是一个VHDL写的数据选择器，正确仿真和验证，是初学者好例子。-This is a write VHDL data selector, correct simulation and verification, is a good example for beginners.
Part1
- Quartus Lab 1 Part 1 solution for the DE2 development board
S4_LCD_VHDL
- 基于ep1c6的vhdl的lcd控制程序实例 -Based on the VHDL ep1c6 the lcd control procedures examples
full_adeeeder
- FPGA上的一个全加器实例程序，通过测试，可以直接运行在fpga开发板上。-A full adder example on FPGA program, through the test, can be run directly on the FPGA development board.
jtagverilo
- Controller Area Network or CAN is a control network protocol from Bosch that has found wide use in Industrial Automation and the Automotive Industry. Most of the patents of CAN are owned by Bosch and although thereisite.