资源列表
FIR
- 用verilog设计的FIR滤波器。滤波器需要很快的处理速度，所以采用了wallace树算法，超前进位加法器-The FIR filter is designed with verilog. To improve the process speed, wallace tree and fast-carrylook-aheadarithmetic were used.
adder
- 用verilog语言描述的二级加法器，通过在ise环境下编译成功。-With the verilog language to describe the two adders, compiled by ise environment successfully.
decode_38
- FPGA/CPLD平台，很好用的3-8译码器源程序。-FPGA/CPLD platforms, the very well with the 3-8 decoder source.
Avalon_VGA_Controller
- Vga Controller source code for Altera FPGA
MCS51_cpld
- VHDL语言编写的cpld与51单片机总线通信程序。结果应用证明。-VHDL language of the CPLD and 51 microcontroller bus communication program. Application results prove.
WS2812B_deneme
- WS2812B strip driver sample
test_42(NEW)
- verilog矩阵键盘扫描程序,编写简单易懂，4X4矩阵键盘读取，比通常的编写更加简单-verilog matrix keyboard scanner, writing easy to understand, 4X4 matrix keyboard to read, write more than the usual simple
lab2_tutorial
- 摘自university of waterloo的个别知道笔记，主要关于electrical and computer engineering方面，包括了8-bit hamming的编解码以及使用VHDL的硬件开发
counter
- 这是用VHDL设计的十进制计数器，两个VHDL程序分别说明了out和buffer的区别-It is designed with VHDL decimal counter, the two VHDL procedures were illustrated the difference between out and buffer
ssss
- spartan—3a对ddr2读写控制源程序，有verilog和vhdl版本-spartan-3a ddr2 read and write control of the source, there are versions of verilog and vhdl
Digital-Lock-In-Detection
- 基于数字锁相技术的研究论文 外国权威 很实用很经典-Based on digital phase-locked technique is very useful research papers are classic foreign authority
altfp_mult_abs
- 浮点数 乘法器带绝对值运算 verilog语言编写 可直接调用-Floating-point multiplier verilog language with absolute operation can be called directly