资源列表
zhong
- 基于FPGA的数字时钟，能校时、校分，整点报时。-fpga clock
scrambler
- 通信系统中的加扰与解扰程序，用verilog语言实现，有波形文件可以直接查看功能
FPGA1IIR4
- 关于iir介绍，希望与大家共同提高。对于了解此滤波器的学习以及研究很有帮助，资料的详细功能-About iir introduction, hope we can together. Filter learning for understanding and study of this useful, detailed information on features
ww1
- 本例实现的检测是否有三路信号输入，如果有可输出一个高电平，同时可计算第一路与第三路之间相差的脉冲数，使用vhdl语言与图形结合的方法。-Achieved in this case detect three-way signal input, if there is a high output, while the first road and calculate the difference between the third way of pulses, using vhdl languag
Clk50M_div_1HZ
- Clk50M_div_1HZ，调试已通过，采用计数器分频 此实验采用计数器，将板载的50MHz时钟源分频为1Hz，分频的结果以LED灯的形式显示。下载电路至FPGA后，会发现LED0会以1Hz的频率闪动。-Clk50M_div_1HZ, using counter this study, frequency counter, onboard 50MHz clock frequency of 1Hz, frequency results in the form of LED lights di
high-efficiency-testbench
- 用VHDL编写高效率testbench 中文-Efficient testbench written in VHDL Chinese
Avalon_VGA_Controller
- 基于ALTERA AVALON BUS 的 VGA Controller 设计-ALTERA AVALON BUS VGA Controller
62256
- EPM1270和ram62256的verilog接口程序，用QuartusII编译
LCD
- 基于vhdl简单的液晶显示电路设计(VHDL desingn)-Display circuit design (VHDL desingn) based on a simple LCD vhdl
vending_machine
- 自动售货机模型，可以设置商品价钱及数量。0.5元及1元投币。可以返回最多1.5元。-Vending machine model, can set the price and quantity of goods. 0.5 yuan and 1 yuan coin. Can return a maximum of 1.5 per head.
VGA
- FPGA嵌入式开发的源代码，本实例是实现VGA彩条信号处理-the source file based on FPGA
fsm
- 有限状态机的一种实现框架，更健壮，更易于表达。-An implementation framework of finite state machines, more robust and easier to express.