资源列表
fifo_tb
- verilog implementation of 16X4 fifo with testbench
fft1
- VHDL语言编写FFT源代码 调试可用-FFT VHDL language source code debugging available
VHDL
- 我做的作业，大家可以看看！ -I do homework, we can see! I do homework, we can see!
5t
- sram design is it,u can see its easy ,so i upload it here my frnds it is useful code see this it is in vhdl language
Challenges-in-the-design-of-frequency-synthesizer
- this document discribes the Challenges in the design of frequency synthesizers for wirele-this document discribes the Challenges in the design of frequency synthesizers for wireless
crc
- CRC编程源程序，使用Verilog硬件编程语言进行编程-CRC program source code, Verilog hardware programming language used to program
fir
- FIR滤波器，使用Verilog硬件描述语言进行编程-FIR filter, using the Verilog hardware descr iption language programming
key
- cpld的按键数码管显示程序 用VHDL编程-cpld key digital display program
Virtex-5
- The Virtex® -5 family provides the newest most powerful features in the FPGA market. Using the second generation ASMBL™ (Advanced Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-f
Embedded-Processor-Block
- This reference guide is a descr iption of the embedded processor block in Virtex® -5 FXT FPGAs.
decrypt_controll
- controller for fast_aes128. Sends start and load pulses at a lower clock than main_clk.
downsizer
- A FSM that extracts the 18 LSB out of a 128 bit vector and forwards it as a 18 bit vector.