资源列表
freqdiv
- A frequenzzzy divider that divides the clock signal rate with a factor of 25.
IO_controll
- this a controller, mainly for the nexys2 board based around the spartan 3E fpga from xilinx. controlls various outputs and inputs.-this is a controller, mainly for the nexys2 board based around the spartan 3E fpga from xilinx. controlls various outpu
stoppsignal
- A VHDL module that counts long pulses on the inport counting rising edges.
mc_t
- 利用verilog实现H.264中半像素插值功能。30个周期完成一个4x4块儿的横向、纵向和斜向的插值。-Verilog implementation using H.264 in the half-pixel interpolation function. 30 cycles to complete a 4x4 pieces of horizontal, vertical and diagonal interpolation.
mc
- 通过VHDL实现H.264算法中的半像素插值模块。该模块儿可在30个周期内完成一个4x4块的横纵斜插值。-H.264 algorithm by VHDL implementation of the half pixel interpolation module. The module can be in 30 children complete a cycle of vertical and horizontal 4x4 block Xiecha value.
clk_div
- deviseur de fréquence pour fpga
counter
- counter design in vhdl
S6_LCD_VHDL_2C35
- VHDL语言编写的LCD调试程序供学习用，不具有商业目的-LCD VHDL languages for learning to use the debugger, does not have a commercial purpose
S6_LCD_VHDL_2C70
- 另一个VHDL编写的LCD学习代码，仅供学习，不具有商业目的-Another study VHDL code LCD write, only to learn, not with a commercial purpose
flash_test
- c语言编写的flash调试程序，供参考学习-c flash debugger written for the reference study
Code-ALU16BIT
- Code ALU 8 bit vhdl arith and logic
VHDLvote7
- VHDLvote7是一个VHDL的投票程序，是我做的课程设计题目，编译通过并在实验板上运行成功-VHDLvote7 s always a VHDL program, with the time when minutes and seconds, and the digital display, is the subject of the curriculum design I do, compile and run successfully in the experimental board