资源列表
crc_eth
- Verilog code to add a CRC field at the end of an ethernet frame.
fga
- FPGA的内建自测试的实现FPGA implementation of built-in self test-FPGA implementation of built-in self test
Broadbction
- FPGA宽带数据采集时钟相位校正方法Broadband data collection FPGA clock phase correction-Broadband data collection FPGA clock phase correction
FPAAcuit
- FPAA石英音叉陀螺的驱动与解调电路设计FPAA quartz tuning fork gyroscope drive and demodulation circuit-FPAA quartz tuning fork gyroscope drive and demodulation circuit
sevenvote
- 一个七人投票表决器，基于VHDL语言，当多数信号为1时输出为1，多数为0时输出为0-A seven-vote device, based on the VHDL language, when the majority of the output signal is 1 to 1, most of the output is 0 0
30daojishi
- 30秒倒计时器，基于VHDL语言。具有循环计时功能，-30 seconds countdown timer, based on the VHDL language. With a cycle time function,
add8(2)
- 一个基于VHDL语言的8位加法器，有进位功能。-A language based on VHDL 8-bit adder, a carry function.
verilog-
- Verilog HDL设计方法详细教程，简单易懂，容易上手-Detailed tutorial Verilog HDL design, easy to understand, easy to use
demo18_key_seg_verilog
- demo18 按键数码管实验 按下S3,S4,S5，S6按键后，数码管显示不同的数字-demo18 press the button digital control experiment S3, S4, S5, S6 button, digital display different figures
demo17-7seg4_verilog
- demo17 数码管显示实验 在数码管上显示0-7-demo17 experiment in digital display digital display 0-7
demo1-LampsSequencer
- 流水灯实验 在LED上显示流水灯，新手上路-LED lights on the experiment in water water light show, a beginner on the road
demo6-beep
- demo6 蜂鸣器实验 蜂鸣器演奏音乐-demo6 buzzer buzzer experiment playing music