资源列表
parallel-output-controller-(POC)
- 并行输出控制器，实现CPU与打印机之间的通信，程序基于VHDL语言，内附完整实验报告与仿真图像-The purpose of this project is to design and simulate a parallel output controller (POC)which acts an interface between system bus and printer. The Altera’s Quartus II EDA tool is recommended and provid
cf_fft_256_8
- The fast fourier transfer (FFT) for 256 point use vhdl
CAD-HW
- verilog code for simple project
code
- 波特仪设计与实现，源代码，用单片机 FPGA实现 适合做类似项目的哥们下载！-Porter Instrument design and implementation, source code, suitable for single chip FPGA realization of similar projects with a buddy to download!
UART
- This vhdl code has a simple implementation of an UART receiver. This code was generated march 2011 as a universuty project
Verilog-to-VHDL-translator
- 描述了一个Verilog到VHDL翻译器的设计与实现。首先将Verilog模块转换为中间格式，然后按照预定义的翻译规则，生成功能等价的VHDL设计实体。该翻译器目前只支持Verilog的一个子集。通过Verilog-to-VHDL， 使得在Verilog．VHDL混合设计环境中重用Verilog设计成为可能。-Describes a Verilog to VHDL translator design and implementation. Verilog module into first
0703030106
- 本文描述了汽车尾灯的设计方法及VHDL源代码，包含汽车的行驶、刹车、左转、右转等功能。-This paper describes the design method of car taillights and VHDL source code, including car driving, brake, turn left, turn right and so on.
eda
- 用vhdl语言编写信号发生器,实现不同频率，不同幅度的方波，锯齿波。-signal generator based on vhdl
DianTiKongZhiQi-VHDL
- 电梯控制器VHDL程序，包含记忆，上升，下降，停站等功能，以及超载，故障后报警功能.rar-Elevator controller VHDL program, including memory, up, down, stop and other functions, and overloading, failure alarm. Rar
FIFO
- 运用Verilog 语言对FPGA实现同步的FIFO的数据缓存和传输功能。-FPGA Verilog language used to synchronize the FIFO data buffer and transmission functions.
yiwei
- 运用Verilog 语言实现了4位的一位计数器的设计。-The use of Verilog language, a 4-bit counter design.
REEDSOLOMON
- error correct and detect