资源列表
LIP2321CORE_cpu_local_ram
- CPU Local RAM Verilog Module
bistable_applications_sim
- the file contains some important applications with bistable used in integrated digital circuits
fpu_sub
- verilog code floating point subtraction
fpu_div
- verilog code floating point division
fa0fdm
- 这是很有用的VHDL和VERILOG 的源代码，我是买过的来的，觉得太有用了，特此共享，对于学习OFDM的人来说，是太难得了！-This is useful VHDL and VERILOG source code, I bought in the past, I feel so useful, and hereby share, for the people who study and OFDM, is too hard won!
ug230
- sparten 3E板子的各个模块的功能说明。-sparten 3E board function of each module descr iption.
54764716
- 乘法电路，vhdl写的。用于VHDL基础学习-multiply
FPGA
- 本文采用FPGA来模拟实际的乒乓球游戏。本设计是基于Altera 公司的FPGA Cyclone II 芯片EP2C35 的基础上实现，运用Verilog HDL 语言编程，Quartus II 软件上进行编译、仿真，最终在Altera 公司的DE2 开发板上成功实现下载和调试-In this paper, FPGA to simulate the actual tennis game. The design is based on Altera' s FPGA Cyclone II EP
clock
- 时钟程序，实现ISM电路板自动产生时钟，是某大学的VHDL实验-Clock program to realize the clock automatically generated ISM board, VHDL is a university experiment
SASA
- 串口程序，一共有四个模块名，波特率为1，包括接受，发送模块-Serial program, a total of four module name, the baud rate is 1, including the acceptance, sending module
ov6620_VGA
- 可以实现数字摄像头的输入，在一般液晶上显示-ov6620+vga
S7_PS2_RS232
- 键盘+rs232通信,可以实现按键的通信-ps2+rs232