资源列表
key_test
- Verilog写的案件扫描程序，用xilinx ise5.2-Scanner written in Verilog case, with xilinx ise5.2
mclock
- 用VHDL编写的带闹钟报时功能的数字钟 ，现代数字系统设计作业。 采用文本图形混合输入，在maxplus2 10.0运行通过-Written by VHDL figures with alarm chime clock, modern digital system design work. Graphics mixed with text input, run by the maxplus2 10.0
uart
- 模拟串口程序，VHDL语言编写，带modem。-vhdl
ddc_cic3_hf
- vhdl语言实现CIC滤波器，用于数字下变频-vhdl
mult
- code for multipication
fpu_add
- verilog code floatinf point addation
multiplier
- vhdl code multiplier
DSPprincipalandapplication
- 对通信，电子信息语音传输处理，和dsp应用中一些常用芯片功能，结构，有点，劣势介绍-Of communication, voice transmission of electronic information processing, and application of some common chips dsp function, structure, little, inferior Introduction
exam3
- 对sparten 3E fpga的板子的一个各个功能模块的多功能vhdl程序，包括键盘防抖，数字时钟等-Sparten 3E fpga of the board of a multi-purpose function modules vhdl procedures, including keyboard, image stabilization, digital clock, etc.
display1211
- 在sparten 3E FPGA上的液晶显示器的控制时序verilog程序，可以在液晶屏上显示任意字符-Sparten 3E FPGA in the liquid crystal display on the control of timing verilog program, you can display any character on the LCD screen
Verilog_FPGA_DDS
- Verilog编写基于FPGA的DDS实现-FPGA-based DDS Verilog
EP3C25
- altera公司的EP3C25的官方参考设计，对开发类似型号的产品设计有很大帮助-EP3C25 altera' s official reference design, product design and development of similar models of great help