资源列表
I2C
- I2C的Verilog HDL简单学习程序-The Verilog HDL simple I2C learning process
prbs
- 伪随机二进制序列发生器的Verilog源码，带测试文件，并在FPGA开发板上成功验证-Pseudo-random binary sequence generator Verilog source code, with a test file, and successfully verified in FPGA development board
div_5
- 一种技术分频器的设计，5分频为例，Verilog源码-A technology Divider, 5-band case, Verilog source code
lcd
- SPARTAN 3E 开发板驱动程序 Verilog源码 对于数字电路设计是很好的参考资料-SPARTAN 3E development board driver for digital circuit design, Verilog source code is a good reference
SOCKET
- 基于de2开发板与pc机之间传输的实验，有详细的实验步骤和全面的资料，socket程序-De2-based development board and transfer between pc machine experiments, a detailed and comprehensive information on experimental procedures, socket program
Rake_Receiver
- 用Verilog HDL语言实现一个Rake接收机的最大比合并准则，其中3路输入数据是并行相关输出-Verilog HDL language with a Rake receiver maximum ratio combining criteria, of which 3 related to the parallel input data is output
multi-function_waveform_generator
- 实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 --A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 --各种波形的线形叠加输出。 -4 sine wave to achieve common, triangle, sawtooth, square wave (A, B) the frequency and amplitude controlled output (square wave- A duty cycle is contr
miaobiao
- 1. 设计数码管显示的秒表。 2. 能够准确的计时并显示。 3. 开机显示00.00.00。 4. 用户可以随时清零、暂停、计时。 5. 最大记时59.59.99分钟，最小精确到0.01秒 -1. Design digital display of a stopwatch. 2. Can be accurately timed and displayed. 3. Power Show 00.00.00. 4. Users can always clear, pause, ti
EDA
- 计数器的程序，eda编程用的，vhdl语言编程，大家下载看看吧-Program counter, eda programming used, vhdl programming
cunchuqi
- 利用MAX+PLUS进行存储器设计 并且进行了编译 仿真 得到了波形图-Using MAX+ PLUS for memory design
DE2_Web_Server
- 此文件是altera公司发布的基于DE2开发板的-web例程，能实现DE2开发板与计算机之间的信息传输，采用vhdL语言编写。-This file is Announces altera DE2 development board based on the-web routine, to achieve DE2 development board and the transfer of information between computers, using vhdL language.