资源列表
DE2_NIOS_HOST_MOUSE_VGA
- FPGA VHDL PROGRAM DE2_NIOS_HOST_MOUSE_VGA
DE2_SD_Card_Audio
- FPGA VHDL PROGRAM DE2_SD_Card_Audio
DE2_USB_API
- FPGA VHDL PROGRAM DE2_USB_API
verilog
- 学习verilog的一本很有意义的书，verilog黄金参考指南中文版-Of a meaningful learning verilog book, verilog golden reference guide Chinese
DE2_Synthesizer
- FPGA VHDL PROGRAM DE2_Synthesizer
monidianlu
- 模拟电路，经典书籍，欢迎惠存，希望有助于大家学习-Analog circuits, classic books, welcome Huicun hope will help them to learn
Multibank
- Sample VHDL Coding can used by U
lesson6_pipelining
- Analysis of the MIPS 32-bit, pipelined processor using synthesized VHDL
code
- register file using verilog
alu
- desein a simble 32 bit alu
project3
- mips single cycle cpu
09912007AEScoremodules
- aes descr iption architecture processes vhdl code with pipelining and throughput reduction with an aim to create a faster AES decoding system in FPGA