资源列表
vhdl_primer
- it is the e book of vhdl programming..that describes about vhdl code ,syntax etc
Manchester
- 运行于Altera Cyclone FPGA平台,由VHDL编写的NRZ到曼彻斯特编码和曼彻斯特编码到NRZ解码程序。-Running on Altera Cyclone FPGA platform, consisting in VHDL coding NRZ to Manchester and Manchester encoding to NRZ decoding process.
lab1
- lab1 report, with code -lab1 report, with codelab1 report, with code
EDA.DAC8812
- DAC8812英文资料，内容非常详细。真值表，时序图，电气特性等。-DAC8812 information in English, the content is very detailed.
VHDL_statemachine
- MOORE 和MEALY模型的状态机，用VHDL语言描述，本章讲述状态机实现的原理以及方法，希望对大家有用，同时有练习题和思考题-MOORE and MEALY model state machine, using VHDL language descr iption of the state machine implementation of this chapter describes the principle and method, we want to be useful, while
VHDLscounter
- 通过VHDL自行设计的一个秒表共有4个输出显示，分别为、十分之一秒、秒、十秒、分，所以共有4个计数器与之相对应（3个十进制计数器，一个6进制计数器用来对十秒进行计数），整个秒表还需有一个复位信号和一个精确的10HZ时钟信号。-Of a self-designed by VHDL stopwatch showed a total of four outputs, namely, one-tenth of seconds, seconds, ten seconds, minutes, so a to
verilog.rar
- 《数字信号处理的FPGA实现》（第二版）光盘verilog代码," The FPGA digital signal processing to achieve" (second edition) CD-ROM code verilog
comp4
- 用verilog编了一个比较器，开发环境是xilinx ise10.1-Verilog compiled using a comparator, the development environment is the xilinx ise10.1
digital_clock
- 本程序功能包括时钟计数、可调时、整点报时等。对初学FPGA的同鞋十分有用。程序本人亲自编写、测试，没问题。芯片用的是cyclone3.-The program features include clock counting, adjustable, on the hour when time, etc. For beginners of FPGA with very useful shoes. Program himself write, and test, no problem. Chip u
VHDL-100
- vhdl100例 ，vhdl 语言实例，包括各种逻辑门的构造。-vhdl100 case
ShiftRegCore
- 基于verilog 的移位寄存器sopc软核-verilog based Shift Reg sopc soft core
multi_booth
- booth乘法器,实现普通booth乘法算法(Booth multiplier to implement the common Booth multiplication algorithm)