资源列表
ADSample_FPGA
- 开发环境为QuartusII。这是AD采样的verilog代码部分，在FPGA上硬件实现AD采样的一部分功能-Development environment for the QuartusII. This is the verilog code for part of the AD sample, the FPGA hardware on the part of the function AD sampling
AlteraFPGACycloneDemo1LampsSequencer
- Example shows how to program Altera FPGA Cyclone Family using VHDL Programming Language
KEY-shuzizhong
- 设计按键的挪位，和时钟通过按键进行加减以及复位(Design key position and clock add and subtract and reset)
p2s
- 并串转换模块，内含有另个.vhd文件。一个是自己写的比较简单 另一个是参考的。-And the string conversion module, which contains another one. Vhd file. One is its relatively simple to write the other is the reference.
stopwatch
- 基于FPGA用VERILOG编写的一个跑表程序....可以实现四位计数跑表-FPGA-based preparation of a stopwatch with a VERILOG program .... can achieve four counts stopwatch ...
Intel8080_lattice
- 基于lattice fpga芯片的intel8080总线模块，简单易懂，适合初学者。这个工程在diamond2.0版本编译运行。-Based lattice fpga chip intel8080 bus module, easy to understand for beginners. The project runs diamond2.0 version of the compiler.
09_SDRAM_VGA_Display_Test640480
- 在quartusII的开发环境下，编写的VerilogHDL语言的SDRAM通信程序，欢迎下载，这是基于Crazybingo的板卡环境设计-Under the development environment of quartusII, write SDRAM VerilogHDL language communication program, welcome to download, this is based on Crazybingo board environment design
Synopsys-RTLSystemC
- synopsys的systemc和RTl书籍清晰电子版，专业权威的EDA公司的培训资料-synopsys of systemc and RTl clear electronic version of books, professional authority of the EDA company' s training materials
COMPARATORS
- comparator vhdl code
AD
- 在Quartus环境下，VHDL语言的一个AD转换程序，即128k采样速率的模数转换-Quartus environment, the VHDL language, one of the AD conversion, 128k sampling rate analog to digital conversion
spi_stm32
- 本程序使用verilog hdl 语言编写的SPI程序，可与stm32进行数据的传输-This program uses SPI verilog hdl language program with stm32 for data transmission