资源列表
HDB3
- 针对数字基带传输系统中HDB3信号的特点，采用基于FPGA的Verilog HDL语言，实现HDB3数字基带信号的编码器设计,共有插V、插B、单双极性变换模块，最终能在FPGA实现。-For digital baseband transmission system HDB3 signal characteristics, based on FPGA Verilog HDL language, designed to achieve HDB3 encoder digital baseband si
10_In3Out8
- 基于EP2C8Q208C8N的3入8出程序，对于入门FPGA有帮助-Based EP2C8Q208C8N 3 into eight programs, for the entry FPGA helpful
uartverilog
- RS232接口，有接收器和发送器和分频器，有详细说明-RS232 interface, a receiver and transmitter and the divider, a detailed descr iption
jiaotongdeng
- 用vhdl语言设计了一个交通灯实验 包含了十字路*通灯的转换-Vhdl language designed by a traffic light intersection experiment includes the conversion of traffic lights
rs_encode
- 关于RS（204,188）的编码程序，已通过编译仿真。-On the RS (204,188) of the coding process has been simulated by compiled.
bldcm-control
- 以前做的无刷直流电机控制程序，用VHDL编写的，挺有用-BLDCM control
madadianji_controller
- 使用altera MAX II CPLD 做的马达步进电机控制器。-Motor stepper motor controller using the altera MAX II CPLD to do.
cpld_test
- CPLD 保护电路，编译通过。直接运用-CPLD protection circuit, compile. Directly applied. . . . . .
ILX554B_CPLD
- 用CPLD（EMP240T100C5）产生ILX554B的驱动时序，CCD的驱动时序电路程序。用verilog编写。-Drive timing generator ILX554B with CPLD (EMP240T100C5), CCD drive timing circuit program. Written in verilog.
cpilegame
- cpilegame - cpilegame by varilog
VHDLexample
- vhdl 语言实例，包括各种逻辑门的构造。