资源列表
.tranfervw
- 一款可以生成.vwf的小软件 对编写verilog语言很有用-a software for vwf file of verilog code programming
fft_design_b.tech
- fft design for development in verilog
fifo-verilog
- 用verilog 编写的fifo（先入先出队列）代码 内含测试文件 test bench-First Input First Output programme which designed by verilog codes,including test bench
password-locker
- 简单的单号密码锁程序 在verilog上实现 包括测试程序-simple password locker programme based on verilog, which including test bench
testbench-from-perl
- 直接生成testbench的perl脚本-The software can produce test bench directly by perl
source
- 数据读取源代码，能将各种数据中的杂项去掉，得到所需要的数据-good ok source code
Simulate-CR-XR-EE-KT_2008_004
- Simulate CR XR-EE-KT_2008_004
Bist_codings
- In this paper, we have explained the purpose of FPGA testing. A built-in-self-test (BIST) is one type of testing. This test is performed internally to find any faults within a FPGA chip. This paper explains why testing is important to FPGAs. It also
bist(1)
- In this paper, we have explained the purpose of FPGA testing. A built-in-self-test (BIST) is one type of testing. This test is performed internally to find any faults within a FPGA chip. This paper explains why testing is important to FPGAs. It also
ADCGraph2
- VHDL PROGRAM & LAB SOLUTIONS
VHDL1332351087
- VHDL Concepts and Tutorial