资源列表
ET-T320240AV2_OK
- LCD320240 test Program
Baudrate_Generate
- AHDL语言编写，对输入的晶振频率经行分频处理，占空比可调的分频器-AHDL language, the crystal frequency on the input line sub-frequency, duty cycle adjustable divider
Based-VHDL-Fpga-Development
- 基于Altera FPGA/CPLD的电子系统设计及工程实践书籍源代码-Book source code of Altera FPGA/CPLD-based electronic system design and engineering practice
adc_0804
- 完整的ADC0804VHDL程序代码，在quartus-ii7.2版本上测试通过，数码管显示。-A complete ADC0804VHDL code, quartus-ii7.2 version tested, the digital display.
Trigger
- 各类触发器VHDL源码程序，在quartus-ii7.2版本上测试通过，文件中包括D触发器，JK触发器，RS触发器，T触发器。-Various triggers VHDL source code program in quartus-ii7.2 version of the test is passed, the document includes a D flip-flop, JK flip-flop, RS flip-flop, T flip-flop.
State_Machine
- 状态机的VHDL实现，在quartus-ii7.2上测试通过，文件包括米利状态机，摩尔状态机，ADC0809的状态机实现，序列检测器和定时去毛刺的状态机实现。-State machine code in VHDL,successfully tested in quartus-ii7.2,the file contains mealy state machine,moore state machine,ADC 0809 and sequence detector achieved in state
module000731
- easy learning for embedded beginners
spartan3e_hdl
- xilinx公司开发板内部集成单元模块功能介绍以及VHDL，Verilog实现。-xilinx development board internal integrated unit module functional descr iption and VHDL, Verilog implementation.
2DPSK-linan
- 全数字2DPSK调制解调系统，为VHDL语言。包括512分频器，M序列发生器等。整个过程完成2DPSK的调制与解调。-The full the digital 2DPSK modem system for the VHDL language. Including the 512 divider, the M-sequence generator. The whole process is completed 2DPSK modulation and demodulation.
DDS
- 基于AD9833的DDS模块EDA设计（vhdl）-serial（485 or 232）
lcd1602
- lcd1602芯片实现单片机显示 使用硬件描述语言，程序已经经过调试，可成功运行-lcd display
05_SPWM
- SPWM EVA下面的通用定时器T1工作于连续增/减计数模式，产生三角载波，载波频率为3000Hz，载波比N=60，因此调制波形正弦波的频率为50Hz。本实验中，调制度为0.8。-2812-SPWM EVA the following general timer T1 work/down to count the prototype model, produce the triangle carrier, the carrier frequency for 3000 Hz, carrier th