资源列表
project-mult
- ARRAY MULTIPLIER FOR VLSI
communication-controller
- 该异步通信控制器主要采用状态机设计完成。包括异步发送端和异步接收端。可异步进行信号的收发-The asynchronous communication controller mainly USES the state machine design completed. Including asynchronous the sender and receiver asynchronous. Can signal to send and receive the asynchronous
fenpin11
- 该小数分频器利用VHDL语言，在同一程序中实现了分频比交错、累加器分频两种方式。采用同步时序。-The decimal prescaler use VHDL language, in the same procedure to realization of points staggered, frequency than accumulators points frequency in two ways. The timing synchronization.
bhaskar
- Wireless sensor networks for low power design vhdl
edk
- edk is useful document for interfacing of various a-edk is useful document for interfacing of various app
lcd
- FPGA控制12864液晶显示，本程序已经调试通过，可以根据自己的要求随意变换显示内容。本程序用Verilog编写。-FPGA to control the 12,864 LCD, debugging has passed, can transform reality according to their Chinese characters, written in Verilog program
I8251A
- Verilog 异步串行收发器，收发器的设计，时序状态机的代码编写
I2C
- 以AVR128为控制芯片，通过I2C总线实现数据存储功能-AVR128 is a control chip, and data storage functions through the I2C bus
wp-01133-ip-camera
- Building an IP Surveillance Camera System with a Low-Cost FPGA
target_6
- 通过设计信号延迟的，目标模拟器设计，包括源代码，仿真代码，以及仿真结果图-Through the design of signal delay , the target simulator design , including the source code , simulation code and simulation results in Figure
2011_11_21_EEPROM_WR
- EEPROM读写控制器，源代码，仿真时序图，以及仿真结果-EEPROM read and write controller , source code, simulation timing diagram and simulation results
multiplier
- 32位乘以32位乘法器，由datapath 和控制中心组成，输出64位结果-32bits by 32 bits multiplier