资源列表
m_sequence
- 用verilog语言描述了M序列（伪随机通信）的编码、解码、纠错等功能，本人通过了Quartus II 以及Modelsim的仿真。-Verilog language descr iption of the M sequence (pseudo-random communication) encoding, decoding, error correction, I passed the Quartus II and Modelsim simulation.
edge_detect_p
- 用于检测信号上升沿，输出与时钟相关的正脉冲-Detect the rising edge of the signal
Verilog_module
- micron 1G内存条verilog模型，对应具体信号为MT8HTF12864HZ-800，内存颗粒为MT47H128M8CF-25-micron 1G DDR2 SDRAM verilog module
BRAT
- early branch rename table-store rename table once the branch instruction comes in. Used in out of order pipeline processor
RAT
- rename table, used to rename architecture registers.-In R10K scheme, rename table is used to translate ARN to PRN to eliminate WAW and WAR hazards.
ADC
- xilinx spartan 3e上的A/D转换程序-xilinx spartan 3e A/D conversion process
ISE10.1
- xilinx ISE10.1开发环境指南，叫你如何操作ISE10.1-xilinx ISE10.1
EP2C8
- Xilinx 的EP2C8程序，内含很多个例程，讲解详细，很有用的。-Xilinx EP2C8
adder
- FPGA的adder程序，例程包含源文件。对大家学习FPGA很有用。-FPGA adder program, the routine contains the source files. FPGA is useful for everyone to learn.
aiqingmaimai
- 数字钟蜂鸣器音乐——爱情买卖，很时尚的闹钟音乐代码，经测试，很有感觉。-Digital clock buzzer music- love trading, very stylish alarm clock music code, tested, great feeling.
booth_mult
- 布斯乘法器的verilog实现及仿真文件,使用modelsim仿真-booth mult s verilog and test
streamline_divider
- streamline 除法器，是国外一个工程师所写,verilog语言，modelsim测试-streamline divider