资源列表
Lab3
- This is stopwatch writen in Verilog HDL. Also there is code for 7-segment display decoder. I tested it on ALTERA de2-115 development and education board.
bijiaoqi
- verilog 9位数 3乘3 窗口比较器
decode3to8
- 一个简单的3-8译码器，verilog语言文件-Simple 3-8 decoder, Verilog language
fenpin
- 一个简单的分频器，可实现时钟分频，可修改参数实现不同分频-A simple divider, clock divider, can modify the parameters to achieve different divider
FPGA
- 个人认为是一个非常实用的FPGA入门教程，非常适合初学者学习-Personally think it is a very practical FPGA Tutorial, very suitable for beginners to learn
fangbo
- 一个可切换分频的时钟分频器的verilog语言，可根据具体情况修改参数实现不同的分频-A switchable clock divider divider verilog language, modify the parameters according to the specific circumstances of different sub-frequency
FPGA
- xilinx培训教程以及ISE使用教程 ISE是一个很好的FPGA开发软件
can2rs232
- can转TTL RS232 介绍及源码分享-can to ttl and rs232 codes
jiafa
- 基于QUTER的VHDL言语的加法器设计-Based on the words of the QUTER VHDL adder design
SR
- 基于QUTER的ST器的VHDL语言设计！-Based on the QUTER ST device VHDL language design!
shiyan2a
- 计算机网络组成实验的QUTER的VHDL的程序组列！-The computer network consisting of the experiment QUTER VHDL program group row!
lighting
- This road signal controller. highway and contry road controlling. goooooood!! FULL Verilog source.-This is road signal controller. highway and contry road controlling. goooooood!! FULL Verilog source.