资源列表
JPEG-Camera-Libraries
- library for UART camera
123123
- VHDL课程设计，交通灯的项目文件，已仿真通过。-VHDL course design, the traffic lights project file, already simulation through the.
The-use-of-VHDL-divider-design
- 分频器的各种设计方法， 及源代码，源代码中完成对时钟信号CLK的2分频，4分频，8分频，16分频。-The use of VHDL divider design
cConnvolutiono
- 卷积码编码与维特比解码 当K为7 时 供大家参考-convolutional encoding and Viterbi decoding with k 1 2 7 rate
Adders
- Adders in VHDL code! full adder,bvadder,adder
Counters
- bcdcounter in VHDL, behavioral
se7en
- a seven segment in vhdl code
mult8
- an 8 bit multiplier and its testbench
xapp333
- i2c controller source code. project related
adder
- 用两个方法实现2位全加器，没有错误，仅供参考。-Can realize two eight bits of Numbers is equal, no error, for reference. With two method two QuanJia device without any error, only supplies the reference.
clk
- 通过Verilog HDL实现多功能数字时钟 开发基于FPGA DE0-Verilog HDL Verilog HDL
gcd.cpp.tar
- SystemC Sourcode to get the Greatest Common Divisor out of two numbers.