资源列表
compare
- verilog两个数的比较，由加法器改编而来-verilog comparison
VLSI_4bitadder
- This source is 4bit adder at magic tool sp source file gooood
detector
- this file is detector verilog source and test bench file thank you!
twomux4to1
- this source is 4to1 mux two design. verilog source.
add_sub
- this source is adder_substrate verilog source adder and subatrate mix very gooooood!
watchvhd
- WATCHVHD硬件描述语言(VHDL)是一个顶级的一个停表类型项目。-WATCHVHD is a top level VHDL type project of a Stop Watch.
MIPS_Pipelined_CPU
- MIPS Pipelined CPU written on VHDL with commands, 5 stage pipeline
verilog-reference-guide.pdf
- this ebook is for verilog reference guide for starter and it will help you to learn the language easily.
PassiveDevices.pdf
- thnx, this verilog refernce mannualfor passsive devicesa-thnx, this is verilog refernce mannualfor passsive devicesa
Clock
- VHDL语言编写的数字时钟程序，包括硬件设计的芯片管脚分配和功能代码等。功能包括时间的设定和显示。-VHDL language digital clock procedures, including hardware design, the chip-pin assignment and functional code. Features include time setting and display.
DDS
- 基于FPGA的直接数字频率合成技术的源代码-Direct digital frequency synthesis
lms
- LMS自适应滤波器,verilog语言实现，能实现有符号数的运算-LMS filer