资源列表
Verilog-SRAM
- 用verilog hdl语言编写的fpga与片外sram 的读写控制-With the verilog hdl language fpga sram chip with read and write control
VHDL_SDH
- 现代光纤通信SDH的VHDL源码，实现SDH开销的接收处理。-VHDL source code of modern fiber-optic communication SDH the SDH overhead of receiving and processing.
Reg-vs-Wire
- This book explains about difference between REG and WIRE in Verilog.
verilog
- 电子钟Verilog语言-电子钟Verilog语言。。。。。。。。。。。。。。。。
ADDER
- verilog DHL编写的一位全加器，编译通过。稍作修改便可编程任意位加法器。-verilog DHL write a full adder, compiled by. Slight modifications can be programmed any adder.
Design_Compiler_FPGA_Design_Flow
- 这是关于如何使用Design Compiler_FPGA Design Flow 软件的说明书。
sort4
- 将给出的数据进行由大到小排列，其中附有modelsim仿真程序-Descending arrangement of the data given
full_case_parallel_case
- 有关综合时full_case，parallel_case用法-For consolidation full_case, parallel_case usage
dianzhen
- 16*16点阵屏程序 可实现输出字型 字形变换 字形移动-16* 16 dot matrix display program can be shaped to achieve the output font glyph transformation moves
chufaqi
- 由verilog语言编写的同步触发器，可实现同步置零-failed to translate
IASKK-OOK-FSKn
- 包含BPSK，ASK，FFSK的数字仿真系统源代码 -Digital simulation system source code with BPSK, ASK, FFSK
yingjiandianziqingxitong
- 硬件电子琴系统设计，能实现语音播放功能，基于vhdl和quartus2，-Organ system hardware design, to achieve voice playback, based on the vhdl and quartus2,