资源列表
any-fre
- 任意分频，小数分频，计数分频的源代码，直接使用的模块，，已经在开发中使用过的IP包-Any frequency, fractional frequency count divided by the source code
test-bench
- 如何编写测试文件，，test bench的编写方法和是列，，总结的非常好的东西-how to code test bench in verilog
AvalonInterfaceSpecification
- Avalon Bus interface specification
Camera_FPGA_Interface
- CMOS Camera interface with FPGA
VerilogQuickRef
- Verilog HDL Quick reference book
WishboneSpecification
- WISHBONE Bus specification
led
- 本实验完成发光二极管的循环点亮实验，由于输入晶振为20M，分频得到count1信号，故每间隔约1S彩灯循环移位一次。 也可以外接32768hz的晶振经4060分频后的1HZclk输入，自己可以尝试改变实验，加以练习。-In this experiment completed the cycle of light-emitting diode light experiments, as a result of the importation of crystal for the 20M, sub-
VHDL-program--samples-book
- VHDL程序实例集，其主要内容包括：用VHDL设计的组合电路、时序电路、数字综合电路、电路图输入法要领概述、实用VHDL语句等。-VHDL instance set, the main contents include: VHDL design of combinational circuits, sequential circuits, digital integrated circuit schematic input method essentials outlines, practica
dac_test
- DAC_TLC5620测试模块，verilog语言-module of texting DAC_TLC5620
clock_check
- 时钟检测,检测时钟的精度，确保时钟没有问题。测试电路，很好用-time test
ram
- 基于FPGA的rom程序（verilog）-rom procedure
quartus-ii-automatically-assign-pins
- quartus ii 中自动分配管脚的三种方法-quartus ii automatically assign pins are three ways