资源列表
i2c_core_v02
- I2C FPGA代码，支持master和slave-I2C FPGA code to support master and slave
m_sequencer
- m序列发生器，长度可以变化，此处使用长度为40 的移位寄存器。反馈函数使用的是：x40+x5+x4+x3+1-m sequence generator, the length can be varied. here the length of the shift register is 40. Feedback function : x40+ x5+ x4+ x3+1
DE2_lab_exercises
- Altera DE2 原装光盘附带 案例教程 手把手教 十个实验 verilog hdl/vhdl-DE2_labs_ exercise with verilog/vhdl
BeijingUniversityTutorialforVerilog
- Verilog超详细教程，北大微电子系硬件设计入门教程。-Super detailed tutorial Verilog, hardware design, Department of Microelectronics, Peking University Tutorial.
circle
- VHDL routine to draw a circle using the midtpoint algorithm.
fir
- 11阶的FIR 数字滤波器-11-order FIR digital filter
chengfaqi.doc
- 设计一个两个5位数相乘的乘法器。用发光二极管显示输入数值，用7段显示器显示结果。乘数和被乘数分两次输入(verilog语言实现)-Design a multiplier of two 5-digit multiplication. Enter the value with the light-emitting diode display, with 7-segment display shows the results. Multiplier and the multiplicand input
chuankou
- 实现串口通信:包括发送，接收，时钟以及顶层模块-function of Serial Comunications
CPU
- 一个完整的流水CPU设计，quartus平台，Verilog实现-CPU design a complete water, quartus platform, Verilog realization
simple_spi_top
- 简单的SPI接口控制器代码。Verilog-A simple SPI interface controller code. Verilog
ddr
- DDR SDRAM 控制器 VHDL代码，可支持32bits数据总线-VHDL code for DDR SDRAM controller, supporting 32bits data bus
jpeg_verilog
- Jpeg压缩的Verilog代码，小图片-Jpeg compression of the Verilog code