资源列表
DIFF
- 基于FPGA的DIFF详细设计方案（附带详细设计方案及代码）-FPGA-based DIFF detailed design (with the detailed design and code)
labmic_soc
- SoC and FPGA desgin
seg
- FPGA简单程序，可实现一位数码管显示，从0到9 的循环显示-FPGA simple program, enabling a digital display, the display cycles 0-9
Xilinx-ISE-Simulator-(ISim)-VHDL-Test-Bench-Tutor
- Xilinx ISE Simulator (ISim) VHDL Test Bench Tutorial
cnt_for_sim
- 采用VERILOG语言的计数器的设计，经过前仿和后仿，仿真波形正确，适用于初学者学习VERILOG语言-Using VERILOG design language of the counter, through the imitation of pre-and post-simulation, the simulation waveform is correct, for beginners to learn the language VERILOG
Design-used-in-traffic-lights-
- 设计的交通灯应用在两条主干道的汇合点形成十字交叉路口，为确保车辆安全，迅速地通行，在交叉道口的每个入口设置了红，绿，黄三色信号灯。红灯亮禁止通行，绿灯亮允许通行，黄灯亮则警告行驶中的车辆，并让它们有时间停靠到禁行线之外。--Design used in traffic lights the confluence of two main roads cross the intersection form, in order to ensure their safe and prompt acces
source
- ModelSim对Altera设计进行功能仿真的简单操作步骤-modelsim simulation
lab_simulation
- verilog 开发的，模拟CPU流水线操作的工程设计。-verilog developed to simulate the engineering design of CPU pipelining.
fsm
- 检测连续3个1的状态机的VHDL代码，输入11111则输出00111，ISE可以编译仿真，运行-Detecting consecutive three one state machine VHDL code, enter 11111 Output 00111, ISE can compile simulation run
kwadrat
- one of example of VGA program
Key_Uart
- 我写的将PS/2键盘按下的值通过串口发送出去。-I wrote to PS/2 keyboard pressed values sent through the serial port.
lab4_2
- 脉冲宽度测量，按下按键开始脉冲宽度的测量，并设计有复位溢出信号，采用状态机模块化设计方法-Pulse width measurement, press the button to start measuring the pulse width, and the design of the overflow reset signal, using the state machine Modular Design