资源列表
seg7
- 了解七段数码管的原理，用VHDL语言来实现点亮七段数码管-Understand the principle of seven-segment digital tube, with the VHDL language to realize the seven-segment digital tube light
modelsim_guide_cn
- modelsim操作指导 很适合入门 有实例-modelsim operation guidance is very suitable example of a portal
fpgaads18b20
- 基于fpga和ds18b20的多路温度测量系统的设计 来源：万方-Fpga-based and multi-channel temperature measurement ds18b20 System Source: Articles
JIANCHE
- 本设计是一个序列检测器，能够检测11位长的系列信号，根据需要可适当扩展其序列长度-The design is a sequence detector, can detect a long series of 11 signals, according to the needs may be appropriate to expand its sequence length
VGA
- 采用Verilog hel语言实现VGA的驱动，非常实用的源程序，有工程，晶振为有源晶振50的-Verilog hel VGA
dct.rar
- 离散余弦变换的设计源代码以及测试源代码和仿真图,Design of discrete cosine transform source code and test source code and simulation plan
No.4
- 使用C8051F005开发板，控制FPGA和高速DA来DDS，两路DDS输出，90或180或0相差-Using the C8051F005 development board, the control FPGA and high-speed DA to DDS, two DDS output, a difference of 90 or 180 or 0
VGA
- VGA显示的例子（VHDL语言），实现彩条显示，按键reset实现切换功能。
SystemC-UART
- 基于SystemC的Uart模型-----文档-SystemC the Uart model of----- document
demo2-seg1
- 实现彩灯控制和图形化输出，属于自动化行业的一些源程序-Lights to achieve control and graphical output, are some of the automation industry source
measure
- 用ＶＨＤＬ语言编写一个状态机电路，可实现对脉宽的测量-VHDL language with a state of electrical and mechanical way, enabling the measurement of the pulse width
LAB27
- 基于FPGA的1K分频模块，输入为24MHZ的时钟信号-1K points frequency FPGA-based modules, the clock signal input 24MHZ