资源列表
seven-segment-decoder
- 简单的七段译码器的verilogDHL代码·虽然很简单 但是希望能到这学习到更多的东西-Simple seven-segment decoder verilogDHL code although very simple but hope to learn more things that
DFF12
- 简单modelsim testbench测试工程，包含源码和testbench文件-Modelsim testbench simple test project, including source code and testbench files
SPIcontroler
- spi控制器，crc模块，top模块，crc测试模块，数据传输测试模块-spi controler
fpga_uartrw
- FPGA的uart控制器的verilog源程序，在cyclone II EP2C8Q208上调试运行成功-FPGA s UART controller Verilog source code, in cyclone II EP2C8Q208 debugging run successfully
counter
- simple counter I hope that will be useful. written in class at school I hope that is useful for all concerned
RIPController
- 基于USB接口的发排卡设计,FPGA + Cy7c68013 + SDRAM-Based USB interface Fapai card design
PS2_Demo
- lease read your package and describe it at least 40 bytes in English. System will automatically delete the directory of debug and release, so please do not put files on these two directory.
code
- Verilog 代码 读写时钟同步 复杂三台总线建模-Verilog code to read and write three bus clock synchronization modeling complex
w5500_spi_fpga
- 共两个文件，一个是对网络芯片W5500进行控制的master spi接口，另一个是w5500命令控制逻辑，命令格式按照w5500芯片的要求，分为地址段，控制段和数据段进行统一控制。此外提供w5500芯片初始化及读写控制流程图。-A total of two documents, one is the master SPI interface for network control chip W5500, the other is a w5500 command control logic, co
vhdl2
- VHDL Language Reference courses part2
FFT
- 适用于FPGA的SOPC方面的元器件添加，如COMPNENT
VHDL-3BCD
- 3位BCD码的计数显示电路。BCD码计数电路从0计到9然后返回到0从新计数。3位BCD码计数器可以实现从0到999的十进制计数。要将计数过程用七段显示LED数码管显示出来，这里采用动态分时总线切换电路对数码管进行扫描，对数码管依次分时选中进行输出计数的个、十、百位的数据。-3 BCD code count display circuit. BCD code counting circuit count from 0 to 9 and then back to 0 from the new cou