资源列表
UART
- 用硬件描述语言实现的uart的IPcore，有详细的注释和测试文件-Hardware descr iption language of the H.264 encoder, detailed notes and test files
Microprocessor_Design_VHDL
- Microprocessor design using VHDL
HdlChipDesignBook
- hdl design book for vhdl and verilog
ARINC818DESIGNGUIDE
- implementation of arinc818
8051
- 51ip核 用vhdl编写 在迅雷上下载-51 ip core write with vhdl
4
- VHDL CODE FOR stepper motor control
eda-2009
- 9600波特率的串行口VHDL接收和发送模块，两个模块既可以单独使用。-VHDL 9600 baud serial port receive and transmit modules, two modules can be used alone.
PipelineSim
- 这是用VerilogHDL写的一个MIPS处理器。-It is written with a MIPS processor VerilogHDL.
fifo_8_8
- 该程序实现的是8*8位的先进先出队列功能的存储器，已成功通过仿真。-Implementation of the program is 8* 8 bit FIFO queue memory function, has successfully passed the simulation.
rom_3_4
- 该程序实现的是3输入4输出的只读存储器的功能，已通过仿真验证。-Implementation of the program is 3 input 4 output of the read-only memory function, has been verified by simulation.
multiplier_10_1
- 乘法器（被乘数、乘数均为4bits,经仿真通过）-This is a code of multiplier with both 4_bit multipliand and 4-bit multiplier.The code has been simulated successfully.
password
- 完成开锁、超时报警、超次锁定、管理员解密、修改用户密码基本的密码锁的功能-Completion of lock, time out alarm, lock and Ultra, the administrator decrypt, modify the user password lock function of the basic