资源列表
wp-01044
- FPGA power managment
key_scan
- FPGA矩阵键盘扫描，是三乘以四规格的。对单片机和FPGA都适用-FPGA matrix keyboard scanning
digital_clock
- 用Verilog HDL 设计一个多功能数字钟，包含以下主要功能： （1） 计时，时间以24小时制显示。 （2） 校时， （3） 跑表：启动、停止、暂停 -Verilog HDL design with a multi-functional digital clock, includes the following main functions: (1) time, time to 24-hour display. (2) school, (3) stopwatch: start
dma
- This direct memory access (DMA) source code.-This is direct memory access (DMA) source code.
HDL_Chip_Design
- HDL Chip Design --- A Practical Guide for Designing, Synthesizing & Simulating Asics & Fpgas Using Vhdl or Verilog (EBook)
Digital_Design_with_CPLD_Applications_and_VHDL_By
- Digital Design with CPLD Applications and VHDL (EBook)
b
- vhdl code of multiplier
a
- booth multiplier vhdl code
UART_VHDL
- 特别适用于TI C6000 DSP扩展UART的VHDL源代码。-a VHDL source code specially for TI C6000 DSP to extend UART
cpu_0
- cpu core!! cpu proccesor!
sys_cpt
- 10.0 quartus 的破解文件，把这个文件替换就可以了 -10.0 quartus the crack file to replace the file on it