资源列表
debounce1
- Debouncing Circuit implementing the Testing Circuit show in the Illustration 1. The input of verification is from a push button switch. In the lower part, the signal is first fed to a debouncing circuit and the to a rising edge detector.
edk_intro_1
- SpeedwayDesign Workshop的EDK完整设计流程参考，包括处理器介绍、总线结构、BSB介绍和执行、添加IP核、创建软件工程： • Xilinx processor solutions • Processor bus structures and typical systems • Development tools • Base System Builder (BSB) • Lab 1 –Part 1 &
edk_intro_2
- Speedway Design Workshop参考设计，定制IP和MicroBlaze调试环境专题。 经典，一步到位！-Speedway Design Workshop™ Featuring Custom IP Creation and MicroBlaze Debug Environment： Utilize the Xilinx embedded systems tools to –Create a custom IP core –Integrate the
FPGA-Debug-Reference-Manual
- FPGA调试基础知识，中文版应用指南，简化Xilinx和Altera FPGA调试过程-FPGA Debug Reference Manual
UG642_psf_rm
- UG642：平台规范格式参考手册，EDK13.4,2012年1月18日，包括EDK平台下的MHS, MPD, PAO, MUI, BBD, MSS, MLD, MDD, XBD等平台规范格式-UG642：Platform Specification Format Reference Manual Embedded Development Kit(EDK) 13.4 UG642 January 18, 2012
asyncfifo
- 异步fifo，使用双端口RAM作为memory-asynchronous fifo
VHDL-node
- VHDL简单程序 包括简单的与门 非门 以及138 等 适合初学者使用-this is VHDL
scaler
- 针对视频数据的ZOOM IN/OUT模块， 插值算法为双线性或最邻近可选。-For video data ZOOM IN/OUT module, Interpolation algorithm for bilinear or nearest neighbor optional.
nandflash
- i am very handsome and very clever
New-Folder
- nhu lai than chung nhu con ga
mux21a
- 应用QuartusII 完成基本组合电路设计-The application QuartusII completion of basic combinational circuit design
Verilog-HDL-Design
- FPGA入门的，云创工作室很好地一本书，主要以XILINX公司的芯片为主!-A very good book from Yunchuang studio for FPGA newer,and this book mainly talks about the verilog HDL and the XILINX FPGA!