资源列表
shouhuoji
- 自动售货机相关文献，VHDL代码，仿真实验和EDA实验-Vending machine related literature, VHDL code and EDA experiments, simulation experiment
mul1617
- 采用verilog RTL级语言，实现了有符号的16位乘17位的乘法器。特点是：采用流水的结构，可以在一个周期内处理完数据。通过QuartusII和Modulesim的功能仿真和时序仿真，并得到正确结果。-Realize the signs of 16 of the 17 patients take on time-multiplier. Features are: the structure of water, can be in a cycle processes the data. Thr
EDAhandbook
- 集成电路设计中EDA电路设计使用教程，学生用-Integrated circuit design in EDA circuit design using the tutorial,for students
counter_up_down
- VHDL语言写的可逆计数器，两路输入，可加可减-VHDL language of the reversible counter
VHDL
- VHDL学习的课件，适合初学者学习，需要的可以-VHDL learning courseware, suitable for beginners to learn
VHDL-Programming-By-Examples
- some example in VHDL code. maybe useful for everyone
FPGA-implementation-of-digital-filters-synthesize
- implement digital filter book. very useful.
Verilog-digital-system-design-RTL-synthesis-testb
- verilog book. RTL sysnthesis testbech
Verilog-HDL---A-Guide-to-Digital-Design-and-Synth
- guide to digital design with verilog.
DE1_UserManual_v1017
- this is a example about coding stype of vhdl
The.Verilog.Hardware.Description.Language.Fifth.E
- the verilog language! a very famous book.
counter
- this source is a counter vhdl project :)