资源列表
FPGA_A.Thien
- stop – watch (verilog)
affich_vga
- this is a file about displaying vga with vhdl
Project
- verilog code for misr
cpld1
- 通过DSP控制CPLD与网口，灯及USB接口芯片的通讯与指示-CPLD and DSP control network through the mouth, lights and USB interface chip communication and instructions
61EDA_B365
- 乒乓球游戏电路设计 VHDL eda技术 课程设计-VHDL eda table tennis game circuit design course design
DA-FIR
- 采用DA算法实现FIR滤波器的设计实验原理建模仿真-DA algorithm using FIR filter design principles of modeling and simulation experiments
dc1
- 40hz sharp with low space and maja -40hz sharp with low space and maja maja
8398
- IT IS A GUNMUT SO WAS IN THE EVENING SEMESTER ARE TOGGLED IN WHAT AREA IN THIS THE SURITY GAVE WAS WRITE IN THAT
mt48lc4m16a2
- 模拟micron的sdram的 VHDL 代码，用于验证自己的sdram控制器。-Micron sdram the VHDL simulation of the code used to validate their sdram controller.
DCT2
- 2 维 DCT的VHDL实现以及 测试代码 ， -2-D DCT of the VHDL implementation and test code
noclip1
- cheats for counter stike coundition zero-cheats for counter stike coundition zero...
codes
- EFFICIENT VLSI ARCHITECTURE FOR VIDEO TRANSCODING PROCESSING ELEMENT