资源列表
traffc_lght
- my project code of traffic light controller in vhdl
MA_HOA_MANCHESTER
- MANCHESTER ENCODING IN VHDL
Timer
- 计时器的设计，在Quartus II上运行通过，FOR NJU Cser。使用了signaltap-The design of the timer, run by the Quartus II, FOR NJU Cser. Used signaltap
Counter
- 计时器的设计，在Quartus II上运行通过，简单易用，主要是For NJU CSers-The design of the timer, run by the Quartus II, easy to use, mainly For NJU CSers
I2C_Verilog_Model
- 该源程序包是I2C的Verilog语言模型，包括以下4个部分：RTL源代码，测试平台，软件仿真代码，说明文件。-This source package is I2C bus model based on Verilog language. It has the following 4 parts: RTL code, testbench, sofeware simulating code, help document.
fpga
- 基于FPGA的信号调制，可产生正弦波，并进行ASK调制和AM调制-FPGA-based signal modulation, can produce sine wave, and the ASK modulation and AM modulation
sirenqiangdaqi
- 设计一个4人参加的智力竞赛抢答计时器。电路具有回答问题时间控制功能。-4 participants to design a quiz answer in timer. Time control circuit has functions to answer questions.
Final
- This module contains a digital clock which can enables clock setup option and up to four alarms. This was targeted Virtex-5 FPGA (ML501) and interfaced with LCD display. and center, north and east push buttons.
AHB_to_Wishbone_Verilog
- 该源代码包是AHB总线到Wishbone总线的交接器，包括以下4个部分：RTL源代码，测试平台，软件测试程序，说明文档。-This source package is the AHB bus to Wishbone bus bridge(wrapper).It has the following 4 parts: RTL codes, testbench, software simulating files, help documents.
2to10
- 2 to 10 bcd under vhdl langage in maxplus2 good one
pid
- it is a matlab program for PID controller, which forms one of the basis system in control system.
FPGA
- 一些常用的源程序，有IC2总线，万年历等5个源代码。希望能对各位有帮助。-Some common source, there IC2 bus, calendar and other 5 source code. Hope you can help.