资源列表
lfsr_randgen
- randomly generate the input valuse
VerilogHDL_Synthesis
- VerilogHDL_Synthesis_A_Practical_Primer，一本经典的verilog教程，详细介绍了可综合的verilog，对于做硬件的很有帮助-VerilogHDL_Synthesis_A_Practical_Primer, a classic verilog tutorial introduces synthesizable verilog, very helpful for the hardware to do
limit_vhdl
- pid控制期中的限幅部分，还有位置式pid代码。从参考书上摘录下来的-pid control clipping part of the period, as well as positional pid code. Down on the extract from the reference
phone
- 模仿电话拨号，并且有晶体管显示输入的数字-Imitation of dial-up, and there are number of transistors display input
FSM
- 用程序实现状态机功能，有限状态机是指输出取决于过去输入部分和当前输入部分的时序逻辑电路。一般来说，除了输入部分和输出部分外，有限状态机还含有一组具有“记忆”功能的寄存器，这些寄存器的功能是记忆有限状态机的内部状态，它们常被称为状态寄存器。在有限状态机中，状态寄存器的的下一个状态不仅与输入信号有关，而且还与该寄存器的当前状态有关，因此有限状态机又可以认为是组合逻辑和寄存器逻辑的一种组合。其中，寄存器逻辑的功能是存储有限状态机的内部状态；而组合逻辑有可以分为次态逻辑和输出逻辑两部分，次态逻辑的功能
sell
- Verilog 实现自动售货机，现在，自动售货机产业正在走向信息化并进一步实现合理化。例如实行联机方式，通过电话线路将自动售货机内的库存信息及时地传送各营业点的电脑中，从而确保了商品的发送、补充以及商品选定的顺利进行-CLK: standard clock signal, in this case, the frequency for 4Hz Now, the vending machine industry is on her way to the information and fur
shiyanshu
- 对于初学VHDL语言的实验丛书，个人认为对于初学者很有帮助。-VHDL language test for the beginner series, personally think very helpful for beginners.
SPI_system
- This a SPI for DE_2 board.The file sampling frequency is 20Khz and board frequency used by this 27Mhz.The slaver chip is MCP2302 working under 3.3V.Finally the input analogue voltage for CH0 is between 0V and 3.3V -This is a SPI for DE_2 board.The fi
ass1_2_hamming
- Hamming codes are a class of binary linear codes. They can detect up to two simultaneous bit errors, and correct single-bit errors. In particular, a single-error-correcting and double error detecting variant commonly referred to SECDED.-a) Develop a
ass1_3_safe
- The objective of this project is to design and implement the controller for an electronic safe. You will interface a 16-button keypad to the NIOS boards. The combination code of the safe will be the last “X” digits ) of 8 digits.-The objective of thi
gap_finder
- Design a sequential machine that finds the size of the largest gap between two successive 1s in a X-bit word. Partition the design into a state machine controller and a datapath. The datapath accepts the X-bit word and produces an output word whose v