资源列表
D_chufaqi
- 用Verilog语言写一个D触发器。在时钟上升沿触发和在时钟下降沿触发。-Using Verilog to make a trigger or flip-flop.
booth
- 8位改进型booth算法的verilog源代码-8bit booth verilog
register
- 用Verilog语言写一个简单的移位寄存器，可以进行算术移位和逻辑移位。-Verilog language used to write a simple shift register, can be arithmetic shift and logical shift.
Vr74x163
- 用Verilog HDL语言写一个计数器，每当时钟到来时计数器加1.-Verilog HDL language used to write a counter, when the clock arrives counter plus 1.
light_state_machine
- 用Verilog HDL语言写一个雷鸟车灯控制器。汽车工作状态有：空闲，左转弯，右转弯，告警。-Verilog HDL language used to write a Thunderbird lights controller. Working state vehicle are: idle, turn left, turn right, alarm.
traffic_light
- 用Verilog HDL语言写一个交通控制灯的状态机。十字路口，红绿灯，带倒计时功能，也可以自行变换亮灯时间。-Verilog HDL language used to write a traffic control light state machine. Intersections, traffic lights, with the countdown function, you can also change their own light time.
guess
- 猜谜游戏。用Verilog HDL语言写一个猜谜游戏，若猜中是哪个灯亮，则胜出。-Guessing game. Verilog HDL language used to write a guessing game, if they correctly guessed which light is the winner.
UART_communication
- it s a document where described rs232 communinication between pc and fpga . it describe the vhdl structure of uart driver in fpga that allow communication between this devices
fir
- this file contain a descr iption in vhdl of a fir it contain three part well described to similate the behavior of the this type of filter
multiplier
- this document describe a 8 * 8 bits mutiplier with vhdl using booth algorithm and shown all parts of implementing this ip by ise software
Optimatform
- FPGA验证平台的优化设计Optimal Design of FPGA Verification Platform-Optimal Design of FPGA Verification Platform
CPLlication-
- CPLD在直升机操纵台中的应用CPLD Application -CPLD Application in the Helicopter Control Taichung