资源列表
doorlock
- 门锁电路的检测器，可以预先输入密码，当输入数值和密码相同时有灯闪亮显示正确。本程序只有一个文件-Lock detector circuit that can pre-enter the password, the password input the same values and have lights shining display correctly. This procedure is only one file
scroll
- 七段数码管显示，可以循环显示一段数字代码，移位速度可由开关控制。本程序可在basys2板子上跑起来-Seven-Segment LED display, you can cycle through a numeric code, the shift speed by switching control. This program can be run up on the board in basys2
dco_12
- 是一个DCO的VHDL代码，源自Willey的博士论文，很好的一个源码，希望对各位有用。-The VHDL code is a DCO, from Willey' s doctoral thesis, a good source, and I hope you useful.
DigitalClockBasedonVHDL
- 基于VHDL编写的数字钟，可以设置时间、闹钟，实现报时等功能。-Written in VHDL-based digital clock, can set time, alarm clock, to achieve timekeeping functions.
FlashLock_test
- pdf actel fpga verilog FLASH读写-pdf actel fpga verilog FLASH write
Modelsim
- modelsim 的使用说明，新手上手最佳手册-modelsim' s instructions, the best manual for novices to get started
AES_test
- verilog AES解密 ACTEL FPGA-verilog AES ACTEL FPGA
embeddeedsystermSOPCdesignbasedonFPGA
- 介绍了SOC发展状况，并针对 ahera公司 FPGA的解决方案 SOPC进行重点分析 ，重点介绍和分析处理器的关键技术和设计流程以及相关软件。 -Describes the development of SOC, and for the FPGA solution ahera SOPC company to focus on analysis, highlights and analysis of the key processor technology and design processe
CaculatorBasedonVHDL
- 用VHDL编写的计算器，供下载到学习板上使用，芯片型号请在工程中查看。可以实现加减与或比较-Written by VHDL calculator, available for download to learn to use the board, the chip model in the project view. Comparison of addition and subtraction can be achieved with or
my_RAM
- pdf actel fpga verilog ram读写-pdf actel fpga verilog ram read and write
D_latch
- actel fpga Verilog D锁存器-actel fpga Verilog D latch
DFF
- actel fpga D触发器 verilog描述-pdf actel fpga d