资源列表
Ethernet
- Ethernet quick guides
Greedy_Snake_verilog
- 基于FPGA的verilog代码，在Spartan3开发板上实现了传统贪吃蛇的游戏，通过VGA显示在屏幕上。按键控制方向。-This is a FPGA project, which used verilog and implemented the traditional game of Greedy Snake.
shixuluojidianlusheji
- 时序逻辑电路设计，FPGA用途，硬件开发，-Sequential logic circuit design, FPGA applications, hardware development,
async_fifo
- async_fifo，与VHDL相关，硬件开发相关，FPGA相关，够了-async_fifo, and VHDL-related, hardware related to the development, FPGA related enough
ispLEVER71userguid
- 该使用指南适用于初次使用ispLEVER软件或者不常使用该软件的工程设计人员，它可以帮助你去了解不同的处理过程，使用各种工具，以及熟悉ispLEVER产生的各种报告。-The user guide for first-time ispLEVER software or do not use the software engineering staff, it can help you to understand the different processes, using a variety o
sram2lcd
- sram、lcd驱动；将彩条数据写入SRAM，然后反复读出数据显式在tft_lcd上-sram, lcd driver the color of the data is written to SRAM, and then read data explicitly repeated on the tft_lcd
1
- FPGA图像压缩代码，可以在nios2上实现。包括压缩和解压缩-FPGA image compression code that can be realized in the nios2. Including the compression and decompression
xcs30xl
- Xilinx Spartan-XL data book
SynplifyPro_Quartus_v5_v4_1
- Quartus仿真软件SynplifyPro应用指导-Guidance on the application simulation software SynplifyPro Quartus
digital-tube
- 实现开发板上的数码管静态循环显示0~F。通过这个实验，掌握采用Verilog HDL语言编程实现7段数码管显示译码器的方法。-The digital realization of the development board cycling static display 0 ~ F. Through this experiment, using Verilog HDL language to master programming 7-segment display decoder method
3des_vhdl_latest
- 3DES的VHDL IP核，64位 标准FIPS 46-3 NIST,并且使用3组64位密钥-The VHDL implementation 3DES，The core complies with the Triple-DES 64-bit block cipher defined in FIPS 46-3 NIST standard and operates with three 64-bit keys. Functional Descr
vga1
- VGA 接口模块，800*600接口时序verilog实现-VGA interface module, 800* 600 interface timing verilog implementation