资源列表
CoreCFI
- VERILOG编写的CoreCFI实验例程，包括整个工程，可以直接使用-Prepared CoreCFI VERILOG test routines, including the whole project, can be used directly
dc_mult_32by32_ASM
- 一个5级流水线结构的32*32 bits乘法器-A 5-stage pipeline structure of the 32* 32 bits multiplier
cpu
- 8位CISC模型计算机设计，包括加减法存储输出的运算-8-bit CISC model of computer design, including the addition and subtraction operations stored output
8051vlog
- 8051IP核，verilog源代码，包含测试向量，-8051 IP Core verilog code， with testbench
NO2_SWITCH_IF
- swiych_if by vhdl using xlinx
no1_arrengment_if
- no1_arrengment_if by vhdl using xlinx
VGA
- VERILOG编写的VGA实验例程，包括整个工程，可以直接使用-VERILOG VGA written test routines, including the whole project, can be used directly
LCD
- verilog语言编写的LCD读写代码，包括整个工程-read and write languages LCD verilog code, including the entire project
CRC
- CRC校验参考设计Verilog代码 包括所有代码-Verilog code for CRC check reference design includes all the code
Mul16
- 16位高速乘法器,采用booth编码，华莱士压缩，超前进位加法器求和完成-16-bits Multiplier
PLD
- PLD实验代码，包括格雷码计数器、键盘扫描和LED点阵显示、SRAM读写、LCD12864显示汉字。-PLD experimental code, including the Gray code counter, keyboard scanning and LED dot matrix display, SRAM read and write, LCD12864 display Chinese characters.
LcdDisp
- 128*64点阵LCD的Verilog代码，LCD为左右半屏各64*64个点，LCDdatasheet可参考ZY12864D.pdf-128* 64 dot matrix LCD, Verilog code, LCD screen is about half of the 64* 64 points, LCDdatasheet refer ZY12864D.pdf