资源列表
VerilogCode_BCD_counter
- Verilog Code for a BCD counter and it is implemented on Altera DE2 board-Verilog Code for a BCD counter and it is implemented on Altera DE2 board
VerilogCode_8-bit_2to1_mux
- Verilog Code for 8 to 1 multiplexer for the code to be implemented on Altera DE2 board
VerilogCode_7_segment_decoder
- Verilog Code for seven segment decoder for the code to be implemented on Altera DE2 board
sr8
- 8bit移位暫存器 隨著CLK觸發 每次將資料依序輸入暫存器 且為FIFO-8bit shift register with the CLK input is triggered each time the data register and the FIFO order
hdmitx
- hdmi tx solution is from company that can help hdmi design using fpga
fpga_report
- “以FPGA为核心的系统设计” FPGA讲座，主要讲了FPGA的主要应用场合，主要结合国赛中的应用。-" The FPGA design as the core of the" FPGA talks mainly about the main applications of the FPGA, the main race with the application of the country.
mux16_1
- 高速并行，有符号16选一的MUX，完整的VERILOG功能模块和测试平台-High-speed parallel, 16 elections have signed one MUX, a complete functional module and test platform VERILOG
jpeg
- 一个较小的JPEG解码程序，所有代码都在一个源文件中-A smaller JPEG decoding process, all the code in a source file
gcd_lcm
- 求两个100以内整数的最大公约数和最小公倍数，只用加法和减法运算-Find the greatest common divisor of two integers less than 100 and the least common multiple, only addition and subtraction
freq_divider
- 一个时钟分频器，可以实现任意整数倍或者分数倍的分频功能。-A clock divider can be an arbitrary integer multiple or fraction of times the frequency function.
16bitCPU
- 16位的单周期CPU，可以实现R型、I型和J型指令-16-bit single-cycle CPU, can achieve R-, I-and J-type instruction
LCD_KEY
- Verilog代码，由4*4扫描式键盘输入数字或运算符号，数码管上显示数字、同时LCD上显示数字或字符。-Verilog code scanning from 4* 4 keyboard input number or operator symbol, displayed on the digital numbers displayed on the LCD while numbers or characters.