资源列表
parrel_to_serial
- S2p源可以用于实现相关的数据,但不能达到草湖北县外操作-S2p source can be used to implement the relevant data, but cannot achieve grass hubei outside the county operation
RTL8019userbook
- 红色飓风II代-CY1C12设计实例，RT8019网络示例文档-application book of RT8019net control of red-stone ii-cy1c12
l_standard_1c12
- 红色飓风II代-CY1C12设计实例，RT8019网络示例源代码-source code of RT8019net control of red-stone ii-cy1c12
i2c
- I2C的RTL源码，verilog，验证过的-I2C verilog RTL
8088verilog
- intel8088的verilog core ，完整的RTL-intel 8088 verilog core， all RTL
128Msdram_verilog_model
- 128Msdram_verilog_model，可以直接使用，很方便-128Msdram_verilog_model
div8M_v
- 基本的分频器，用于将时钟频率降低一半。包含两个接口，只使用寄存器，未使用线网类型。-The basic divider for halving the clock frequency. Contains two interfaces, using only regs instead of wires.
neek_ocm_spi
- short c++ builder tutorial
veriloghdllicheng135li
- Verilog的应用例程，包含了基本的硬件编程，加法器，触发器-Application of Verilog routines, including the basic hardware programming, adders, flip-flop
bin_BCD
- conversor BCD-7SEGMENTOS
SDRAM-controller-design-FPGA-based
- 基于FPGA的SDRAM控制器设计及应用硕士论文-SDRAM controller design FPGA based
22222222222
- 地址线为8位，数据线为八位的正弦信号发生器，采用文本原理图混合输入的方法。-8-bit address lines, data lines for the eight sinusoidal signal generator, using the text input method for mixed schematic.