资源列表
one_clk
- Verilog 中 1:1 分频 电路，实践中可能会用到，这种方法，我也想了很久 -verilog frequency
lab5_doc
- FPGA很好的实验代码，用verilog进行编写的！-FPGA，used verilog HDL！
VHDL_simple_settable_clock
- 基于Xilinx ISE软件的用VHDL编写的一个简易的可调节时钟，具有时、分、秒功能-Xilinx ISE based,a simple settable clock using VHDL, with hours, minutes, seconds functions
VHDL_decimal_settable_counter
- VHDL语言编写的简易十进制可调节计数器-A simple decimal settable counter using VHDL
fir6dlms
- lms算法，自适应滤波器中使用fir滤波器对信号的码间干扰进行均衡-lms
zzchufaqi
- vhdl 除法器 eda课程设计用。 设计一个两个五位数相除的整数除法器。用发光二极管显示输入数值，用7段显示器显示结果十进制结果。除数和被除数分两次输入，在输入除数和被除数时，要求显示十进制输入数据。采用分时显示方式进行，可参见计算器的显示功能。-divider vhdl eda curriculum design purposes. Design a two five-digit integer divider division. Enter the value with the lig
0792386043
- Rapid Prototyping of Digital Systems
jtd
- verilog编写的交通灯程序。内有波形仿真-traffic light program written in verilog. There waveform simulation
FPGAclock
- FPGA设计中，时钟设计是很重要的一环，本文主要描述了FPGA设计中时钟设计的重要事项-FPGA design, clock design is a very important part, this paper describes the design of FPGA design, the clock on important issues
serialcom
- 串口通信的一个小程序，可以实现与上位机及下位机之间的通信，希望对大家的学习带来帮助-A small program serial communication can be achieved with the host computer and the communication between the lower machine, we hope to bring help to learn
baseband_code
- 利用VHDL硬件语言编写了常用的基带码的产生，Quartus ii 仿真通过。-Written by VHDL hardware language code commonly used in the generation of baseband, Quartus ii simulation pass.
UARTRXTX
- MSP430f449的max232的TX与RX问题解决-MSP430f449 the max232' s problem-solving TX and RX