资源列表
Ts3cc2410PPLLh
- 这个是三星arm9芯片的PLLL源码，不可多的啊 -This is the Samsung arm9 chip the PLLL source can not be more
FDDDDSPLLP
- 一种基于FPGA的新的的DDS+PLL时钟发生器 -An FPGA-based new DDS+PLL clock generator
TCOLLOR_CHAR_h
- 此ip核是xvga视频接口控制器，，主要针对xilinx公司的开发工具 -This IP core is the xvga video interface controller, the main development tool for xilinx
IDCTTzipm
- 改进的DCT算法设计，，veriloghdl实现 -Improve the DCT algorithm design,, veriloghdl to achieve
FffppgajpegP
- 一种基于FPGA的JJPEG图像压缩芯片设计 -Based the FPGA JJPEG image compression chip design
xx
- change path LED8X8 多圖切換-change path led8x8 path change
pinlvji
- 1．基本要求 （1）频率测量 测量范围:1HZ~1MHZ,信号为方波等 （2）周期测量 测量范围:1HZ~1MHZ,信号为方波等 （3）具有显示功能。 -A. Basic requirements (1) the frequency of measurement Measuring range: 1HZ ~ 1MHZ, the signal is a square wave, etc. (2) The cycle of measurement Measuring ra
ssji
- 1．基本要求 （1）频率测量 测量范围:1HZ~1MHZ,信号为方波等 （2）周期测量 测量范围:1HZ~1MHZ,信号为方波等 （3）具有显示功能。 -A. Basic requirements (1) the frequency of measurement Measuring range: 1HZ ~ 1MHZ, the signal is a square wave, etc. (2) The cycle of measurement Measuring ra
ssaszhaohengji
- 1．基本要求 （1）频率测量 测量范围:1HZ~1MHZ,信号为方波等 （2）周期测量 测量范围:1HZ~1MHZ,信号为方波等 （3）具有显示功能。 -A. Basic requirements (1) the frequency of measurement Measuring range: 1HZ ~ 1MHZ, the signal is a square wave, etc. (2) The cycle of measurement Measuring ra
VGAverilog
- VGA scanning programm
stack
- stack code for fpga..using verilog
HDB3(verilog)
- HDB3_verilog编码程序,附有文字解说,格式整齐,便于观看-HDB3_verilog coding procedures